DSPIC30F3013-20I/ML【PDF 11/161 页】IC DSPIC MCU/DSP 24K 44QFN

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PIC18F46J11 FAMILY

DS39932D-page 138

2011 Microchip Technology Inc.

10.3

PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

EXAMPLE 10-3:

INITIALIZING PORTB

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit, RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a POR.

Four of the PORTB pins (RB<7:4>) have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB<7:4> pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB<7:4>)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB<7:4>

are ORed together to generate the RB Port Change

Interrupt with Flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from Sleep mode or

any of the Idle modes. The user, in the Interrupt Service

Routine (ISR), can clear the interrupt using the following

steps:

Any read or write of PORTB (except with the

MOVFF (ANY), PORTB

instruction).

Wait one instruction cycle (such as executing a

NOP

instruction).

Clear flag bit, RBIF.

A mismatch condition continues to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared after one instruction

cycle of delay.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

The RB5 pin is multiplexed with the Timer0 module

clock input and one of the comparator outputs to

become the RB5/KBI1/SDI1/SDA1/RP8 pin.

Note:

On a POR, the RB<3:0> bits are

configured as analog inputs by default and

read as ‘0’; RB<7:4> bits are configured

as digital inputs.

CLRF

LATB

; Initialize LATB

; to clear output

; data latches

MOVLB

0x0F

; ANCON1 not in Access

; Bank

MOVLW

0x17

; Configure as digital I/O

MOVWF

ANCON1

; pins in this example

MOVLW

0xCF

; Value used to

; initialize data

; direction

MOVWF

TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

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